ResearcherID.com
ResearcherID
Giorgi, Roberto
Create a ResearcherID badge for this researcher Go to ResearcherID Labs for this researcher
Close
ResearcherID: A-3419-2009
URL: http://www.researcherid.com/rid/A-3419-2009
Subject: Computer Science; Engineering
Keywords: computer architecture; multiprocessor; cache
My Institutions (more details)
Primary Institution:
Sub-org/Dept: Departmento of Information Engineering
Role:
Past Institutions: University of Alabama in Huntsville; University of Pisa
Description:
 

Publications

My Publications (70)

 
Publication List: View
publication(s)  
First Page Previous Page Page   of  7  Go Next Page Last Page
  Sort by: 
Results per page: 
1. Title: Scheduled Dataflow: Execution paradigm, architecture, and performance evaluation
Author(s): KAVI, KM; GIORGI, R; ARUL, J
Source: IEEE TRANSACTIONS ON COMPUTERS Volume: 50 Issue: 8 Pages: 834-846 Published: AUG 2001
Times Cited: 19
added
01-Mar-09
2. Title: PSCR: A coherence protocol for eliminating passive sharing in shared-bus shared-memory multiprocessors
Author(s): GIORGI, R; PRETE, CA
Source: IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS Volume: 10 Issue: 7 Pages: 742-763 Published: JUL 1999
Times Cited: 7
added
01-Mar-09
3. Title: Trace factory - Generating workloads for trace-driven simulation of shared-bus multiprocessors
Author(s): GIORGI, R; PRETE, CA; PRINA, G; et al.
Source: IEEE CONCURRENCY Volume: 5 Issue: 4 Pages: 54-& Published: OCT-DEC 1997
Times Cited: 6
added
01-Mar-09
4. Title: Effects of instruction-set extensions on an embedded processor: A case study on elliptic-curve cryptography over GF(2(m))
Author(s): BARTOLINI, S; BRANOVIC, I; GIORGI, R; et al.
Source: IEEE TRANSACTIONS ON COMPUTERS Volume: 57 Issue: 5 Pages: 672-685 Published: MAY 2008
Times Cited: 1
DOI: 10.1109/TC.2007.70832
added
01-Mar-09
5. Title: Simulation study of memory performance of SMP multiprocessors running a TPC-W workload
Author(s): FOGLIA, P; GIORGI, R; PRETE, CA
Source: IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES Volume: 151 Issue: 2 Pages: 93-109 Published: MAR 2004
Times Cited: 1
added
01-Mar-09
6. Title: Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload
Author(s): FOGLIA, P; GIORGI, R; PRETE, CA
Source: JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING Volume: 65 Issue: 3 Pages: 289-306 Published: MAR 2005
Times Cited: 0
added
01-Mar-09
7. Title: Boosting the performance of Three-Tier Web Servers deploying SMP architecture
Author(s): FOGLIA, P; GIORGI, R; PRETE, CA
Source: WEB ENGINEERING AND PEER TO PEER COMPUTING Volume: 2376 Pages: 134-146 Published: 2002
Times Cited: 0
added
01-Mar-09
8. Title: Bus Utilization Analysis of Multithreaded Shared-Bus Multiprocessors: Initial Results
Author(s): GIORGI,R.; FOGLIA,P.; PRETE,C.
Source: IASTED Proceedings of 9th International Conference on Parallel and Distributed Computing and Systems (IPDCS-97) Pages: 24-29 Published: 1997
added
01-Mar-09
9. Title: An approach for investigating design and tuning performance of embedded systems
Author(s): GIORGI,R.; PRETE,C.; PRINA,G.
Source: EAEEIE Proceedings of International Conference on Innovation and Quality in Education for Electrical and Information Engineering Pages: G1.15-20 Published: 1997
added
01-Mar-09
10. Title: Trace Factory: Generating Workloads for Trace-Driven Simulation of Shared-Bus Multiprocessors
Author(s): GIORGI,R.; PRETE,C.; PRINA,G.; et al.
Source: IEEE Concurrency Volume: 5 Issue: 4 Pages: 54-68 Published: 1997
added
01-Mar-09
publication(s)  
First Page Previous Page Page   of  7  Go Next Page Last Page
  Sort by: 
Results per page: 
Published by Thomson Reuters