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Shin, Youngsoo
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ResearcherID: C-1621-2011
URL: http://www.researcherid.com/rid/C-1621-2011
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This list contains papers that I have authored.

publication(s)  
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1. Title: Light Interference Map: A Prescriptive Optimization of Lithography-Friendly Layout
Author(s): Shin, YS; Shim, S; Choi, S
Source: Ieee Transactions on Semiconductor Manufacturing Volume: 29 Issue: 1 Pages: 44-49 Published: 2016
Times Cited: 0
DOI: 10.1109/TSM.2015.2512901
added
10-Jun-16
2. Title: One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements
Author(s): Shin, YS; Lin, YS; Kim, JJ; et al.
Source: Ieee Transactions on Very Large Scale Integration (Vlsi) Systems Volume: 24 Issue: 2 Pages: 600-612 Published: 2016
Times Cited: 2
DOI: 10.1109/TVLSI.2015.2409118
added
10-Jun-16
3. Title: Reliable Memristive Switching Memory Devices Enabled by Densely Packed Silver Nanocone Arrays as Electric -Field Concentrators
Author(s): Shin, YS; Joe, DJ; Jung, YS; et al.
Source: Acs Nano Volume: 10 Issue: 10 Pages: 9478-9488 Published: 2016
Times Cited: 0
DOI: 10.1021/acsnano.6b04578
added
19-Dec-16
4. Title: Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization
Author(s): Shin, YS; Kim, S; Kang, S
Source: Acm Transactions on Design Automation of Electronic Systems Volume: 21 Issue: 3 Published: 2016
Times Cited: 0
DOI: 10.1145/2856032
added
19-Dec-16
5. Title: Wakeup scheduling and its buffered tree synthesis for power gating circuits
Author(s): Paik, S; Shin, YS; Kim, S; et al.
Source: Integration-the Vlsi Journal Volume: 53 Pages: 157-170 Published: 2016
Times Cited: 0
DOI: 10.1016/j.vlsi.2015.12.008
added
10-Jun-16
6. Title: Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation
Author(s): Shin, YS; Kim, JJ; Shin, IS
Source: Ieee Transactions on Circuits and Systems I-Regular Papers Volume: 62 Issue: 2 Pages: 468-477 Published: 2015
Times Cited: 1
DOI: 10.1109/TCSI.2014.2364691
added
17-Sep-15
7. Title: An Analytical Approach to Thermal Design and Optimization With a Temperature-Dependent Power Model
Author(s): Shim, SB; Lee, JW; Shin, YS
Source: Ieee Transactions on Circuits and Systems I-Regular Papers Volume: 62 Issue: 3 Pages: 816-824 Published: 2015
Times Cited: 1
DOI: 10.1109/TCSI.2014.2380638
added
17-Sep-15
8. Title: Topology-oriented pattern extraction and classification for synthesizing lithography test patterns
Author(s): Shim, SB; Shin, YS
Source: Journal of Micro-Nanolithography Mems and Moems Volume: 14 Issue: 1 Published: 2015
Times Cited: 0
DOI: 10.1117/1.JMM.14.1.013503
added
17-Sep-15
9. Title: HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning
Author(s): Baek, D; Kim, D; Paik, S; et al.
Source: Ieee Transactions on Circuits and Systems I-Regular Papers Volume: 61 Issue: 1 Pages: 146-159 Published: 2014
Times Cited: 0
DOI: 10.1109/TCSI.2013.2264690
added
02-Jun-14
10. Title: Simplifying Clock Gating Logic by Matching Factored Forms
Author(s): Shin, Y; Han, IH
Source: Ieee Transactions on Very Large Scale Integration (Vlsi) Systems Volume: 22 Issue: 6 Pages: 1338-1349 Published: 2014
Times Cited: 1
DOI: 10.1109/TVLSI.2013.2271054
added
07-Dec-14
publication(s)  
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