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Azevedo, Rodolfo J
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ResearcherID: F-3008-2012
Other Names: R. Azevedo
URL: http://www.researcherid.com/rid/F-3008-2012
Subject: Computer Science
Keywords: computer architecture; embedded systems
ORCID: http://orcid.org/0000-0002-8803-0401
My Institutions (more details)
Primary Institution:
Sub-org/Dept: Institute of Computing
Role:
Description:
My URLs: http://www.ic.unicamp.br/~rodolfo
 
 

This list contains papers that I have authored.

publication(s)  
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1.  Title: Empirical Web Server Power Modeling and Characterization
 Author(s): Piga, Leonardo; Bergamaschi, Reinaldo; Klein, Felipe; et al.
 Source: 2011 Ieee International Symposium on Workload Characterization Pages: 75 Published: 2011
 Times Cited: 3
added
04-Jul-12
2.  Title: Using Multiple Abstraction Levels to Speedup an MPSoC Virtual Platform Simulator
 Author(s): Moreira, Joao; Klein, Felipe; Baldassin, Alexandro; et al.
 Source: 2011 22nd Ieee International Symposium on Rapid System Prototyping Pages: 99-105 Published: 2011
 Times Cited: 0
added
04-Jul-12
3.  Title: A GENERAL IMAGE PROCESSING ARCHITECTURE FOR FPGA
 Author(s): Cappabianco, Fabio; Araujo, Guido; Azevedo, Rodolfo; et al.
 Source: 2009 5th Southern Conference on Programmable Logic, Proceedings Pages: 27-32 Published: 2009
 Times Cited: 0
 DOI: 10.1109/SPL.2009.4914921
added
04-Jul-12
4.  Title: A Multi-Model Engine for High-Level Power Estimation Accuracy Optimization
 Author(s): Klein, Felipe; Leao, Roberto; Araujo, Guido; et al.
 Source: Ieee Transactions on Very Large Scale Integration (Vlsi) Systems Volume: 17 Issue: 5 Pages: 660-673 Published: MAY 2009
 Times Cited: 5
 DOI: 10.1109/TVLSI.2009.2013627
added
04-Jul-12
5.  Title: Characterizing the Energy Consumption of Software Transactional Memory
 Author(s): Baldassin, Alexandro; Klein, Felipe; Araujo, Guido; et al.
 Source: Ieee Computer Architecture Letters Volume: 8 Issue: 2 Pages: 56-59 Published: 2009
 Times Cited: 3
 DOI: 10.1109/l-ca.2009.47
added
04-Jul-12
6.  Title: SPARC16: A new compression approach for the SPARC architecture
 Author(s): Ecco, Leonardo; Lopes, Bruno; Xavier, Eduardo C.; et al.
 Source: Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing Pages: 169-176 Published: 2009
 Times Cited: 4
 DOI: 10.1109/sbac-pad.2009.22
added
04-Jul-12
7.  Title: A Software Transactional Memory System for an Asymmetric Processor Architecture
 Author(s): Goldstein, Felipe; Baldassin, Alexandro; Centoducatte, Paulo; et al.
 Source: 20th International Symposium on Computer Architecture and High Performance Computing, Proceedings Pages: 175-182 Published: 2008
 Times Cited: 0
 DOI: 10.1109/sbac-pad.2008.21
added
04-Jul-12
8.  Title: Instruction Scheduling Based on Subgraph Isomorphism for a High Performance Computer Processor
 Author(s): Santos, Ricardo; Azevedo, Rodolfo; Araujo, Guido
 Source: Journal of Universal Computer Science Volume: 14 Issue: 21 Pages: 3465-3480 Published: 2008
 Times Cited: 1
added
04-Jul-12
9.  Title: A flexible platform framework for rapid transactional memory systems prototyping and evaluation
 Author(s): Kronbauer, Fernando; Baldassin, Alexandro; Albertini, Bruno; et al.
 Source: RSP 2007: 18th IEEE/IFIP International Workshop on Rapid System Prototyping, Proceedings Pages: 123-129 Published: 2007
 Times Cited: 1
added
04-Jul-12
10.  Title: A methodology and toolset to enable SystemC and VHDL co-simulation
 Author(s): Maciel, Richard; Albertini, Bruno; Rigo, Sandro; et al.
 Source: Ieee Computer Society Annual Symposium on Vlsi, Proceedings Pages: 351-356 Published: 2007
 Times Cited: 2
 DOI: 10.1109/ISVLSI.2007.9
added
04-Jul-12
publication(s)  
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