ResearcherID Thomson Reuters  

Shin, Youngsoo
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ResearcherID: C-1621-2011
URL: http://www.researcherid.com/rid/C-1621-2011
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This list contains papers that I have authored.

publication(s)  
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1.  Title: Fast Verification of Guide-Patterns for Directed Self-Assembly Lithography
 Author(s): Shim, S; Shin, Y
 Source: Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume: 36 Issue: 9 Pages: 1522-1531 Published: 2017
 Times Cited: 0
 DOI: 10.1109/TCAD.2016.2629419
added
06-Nov-17
2.  Title: Lithography Defect Probability and Its Application to Physical Design Optimization
 Author(s): Shim, S; Chung, W; Shin, Y
 Source: Ieee Transactions on Very Large Scale Integration (Vlsi) Systems Volume: 25 Issue: 1 Pages: 271-285 Published: 2017
 Times Cited: 0
 DOI: 10.1109/TVLSI.2016.2572224
added
15-Jun-17
3.  Title: Machine Learning-Guided Etch Proximity Correction
 Author(s): Shim, SB; Shin, YS
 Source: Ieee Transactions on Semiconductor Manufacturing Volume: 30 Issue: 1 Pages: 1-7 Published: 2017
 Times Cited: 0
 DOI: 10.1109/TSM.2016.2626304
added
15-Jun-17
4.  Title: Light Interference Map: A Prescriptive Optimization of Lithography-Friendly Layout
 Author(s): Shin, YS; Shim, S; Choi, S
 Source: Ieee Transactions on Semiconductor Manufacturing Volume: 29 Issue: 1 Pages: 44-49 Published: 2016
 Times Cited: 0
 DOI: 10.1109/TSM.2015.2512901
added
10-Jun-16
5.  Title: One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements
 Author(s): Shin, YS; Lin, YS; Kim, JJ; et al.
 Source: Ieee Transactions on Very Large Scale Integration (Vlsi) Systems Volume: 24 Issue: 2 Pages: 600-612 Published: 2016
 Times Cited: 3
 DOI: 10.1109/TVLSI.2015.2409118
added
10-Jun-16
6.  Title: Reliable Memristive Switching Memory Devices Enabled by Densely Packed Silver Nanocone Arrays as Electric -Field Concentrators
 Author(s): Shin, YS; Joe, DJ; Jung, YS; et al.
 Source: Acs Nano Volume: 10 Issue: 10 Pages: 9478-9488 Published: 2016
 Times Cited: 6
 DOI: 10.1021/acsnano.6b04578
added
19-Dec-16
7.  Title: Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization
 Author(s): Shin, YS; Kim, S; Kang, S
 Source: Acm Transactions on Design Automation of Electronic Systems Volume: 21 Issue: 3 Published: 2016
 Times Cited: 0
 DOI: 10.1145/2856032
added
19-Dec-16
8.  Title: Wakeup scheduling and its buffered tree synthesis for power gating circuits
 Author(s): Paik, S; Shin, YS; Kim, S; et al.
 Source: Integration-the Vlsi Journal Volume: 53 Pages: 157-170 Published: 2016
 Times Cited: 0
 DOI: 10.1016/j.vlsi.2015.12.008
added
10-Jun-16
9.  Title: Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation
 Author(s): Shin, YS; Kim, JJ; Shin, IS
 Source: Ieee Transactions on Circuits and Systems I-Regular Papers Volume: 62 Issue: 2 Pages: 468-477 Published: 2015
 Times Cited: 1
 DOI: 10.1109/TCSI.2014.2364691
added
17-Sep-15
10.  Title: An Analytical Approach to Thermal Design and Optimization With a Temperature-Dependent Power Model
 Author(s): Shim, SB; Lee, JW; Shin, YS
 Source: Ieee Transactions on Circuits and Systems I-Regular Papers Volume: 62 Issue: 3 Pages: 816-824 Published: 2015
 Times Cited: 1
 DOI: 10.1109/TCSI.2014.2380638
added
17-Sep-15
publication(s)  
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